As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (FinFET). A FinFET device is characterized by a semiconductor fin that is formed perpendicularly on a semiconductor substrate in order to provide a vertical channel within the FinFET device. This vertical channel, rather than an exclusively planar channel that is present within a planar field effect transistor device, is covered with a gate dielectric, and subsequently also with a gate electrode. The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.
Conventionally, thin vertical fins are formed by one of the following two methods: first, fins are formed by epitaxially growing in-between isolation structure; and second, fins are formed prior to the formation of isolation structures. However, the first method has encountered difficulties of epitaxial structure integrity as device density increase and interval between each isolation decrease making smaller space interval of epitaxial growth; and the second method has encountered problems of different heights of epitaxial structures in different sizes of areas, and thus extra CMP processes are required resulting in increases of material and process costs.
Therefore, how to improve device density and maintaining product performance and lowering manufacturing cost at the same time has become the subject of the present invention.